The present invention relates to nitrogen implantation schemes for creating oxynitride gates of variable thicknesses and/or an oxynitride liner for shallow trench isolation in semiconductor devices.
Integrated Circuit (IC) technology relies on the successful performance of each of its contributing components. Although the technology drivers are typically high performance active devices, the overall success of an IC technology hinges equally critically on good isolation structures (areas that prevent the active devices from interfering with each other). A variety of techniques have been developed to isolate devices in integrated circuits. Among the different isolation structures, shallow trench isolation (STI) has long been viewed as the indispensable device isolation for deep sub-micron technology, because it is free from bird's beak encroachment, field oxide thinning and leakage due to punchthrough. However, STI is more complicated and costly compared to the conventional LOCOS isolations. Therefore, much like "bird's beak" in LOCOS, these problems limit the scaling of the technology.
Conventional shallow trench isolation involves depositing an oxide layer on the surface of a semiconductor substrate, followed by deposition or formation of a nitride layer that is patterned to act as a mask for shallow trench etch. The nitride mask also has a role as a proper substrate for CMP, and preventing further oxidation of the substrate surface where it is masked. The next step involves etching of the shallow trench followed by formation of an oxide liner in the shallow trench. Following formation of the oxide liner, the trench is filled with deposited oxide, and the partly formed device is subjected to CMP to planerize down to the top of the trench and to the substrate layer adjacent to the trench. Next, the p- and n-wells are implanted using n-well and p-well masks on the corresponding sides. Boron is commonly used as a p-well dopant and phosphorus as an n-well dopant.
During subsequent thermal processing steps, boron tends to diffuse out from the p-well into the substrate, towards the shallow trench and segregate into its oxide. Due to this tendency of boron to diffuse and its diffusion dependence on defects in silicon (referred to as transient enhanced diffusion (TED)), the p-well corner bordering on the shallow trench becomes the weak link in the electrical isolation. The remaining lower concentration of boron is easier to invert than the original higher concentration and tends to allow leakage current to flow at lower threshold voltages than the intended higher boron concentration. Keeping boron concentration up at the p-well/STI interface would help isolation dependability. Better isolation in the p-well corner of the trench would allow for narrower trenches as well. This would save space on chips.
A further problem encountered with shallow trench isolations is the so-called reverse narrow channel effect (RNCE), or reverse narrow width effect (RNWE). This effect refers to the problem encountered at the upper comers of shallow trench isolations that interface with channel regions of transistors adjacent to these STIs. Since threshold voltage varies proportionally with transistor width, rounding of the comers of the STI, which occurs when oxidized liners are used in the STI (the thicker the liner the more the rounding; trench linings typically vary from approximately 100 microns to 400 .ANG.), effectively results in a narrower transistor. This reduces the threshold voltage required to turn the transistor on. Thus, RNCE is the decrease of threshold voltage with decreasing channel width due to rounding of the STI upper corners.
FIG. 1 depicts a graph of threshold voltage (V.sub.t) versus channel width (W) illustrating the problem of RNCE. The graph 100 plots three lines. The phantom line 101 represents a flat ideal profile desired by device designers so that control is uniform across the whole width of a transistor. The upper line (curve) 102 represents the voltage threshold profile for a device in which the upper comers of the STI are sharp. The high electric field in these sharp corners collects electrons or holes and therefore more charge at the gate is necessary to invert the channel. Rounding of the comers by applying a STI liner produces the profile of the bottom line (curve) 104. As can be seen in the plot, the threshold voltage decrease for narrow transistors is pronounced. This is the referred to as the RNCE. This RNCE results in difficulties in, for example, design of embedded memory devices.
RNCE is exacerbated by impurity (e.g., boron from the p-well) redistribution at the channel edge caused by the above-noted transient enhanced diffusion (TED). During thermal oxidation, boron migrates into the STI oxide (segregation) and its concentration in silicon is reduced. The corner effect combined with the diffusion of boron in p-wells at the p-well STI interface, combines to have a large effect on threshold voltage in narrow channel widths because the comers on both side of the channel make up a substantial portion of the width of the entire transistor. RNCE frustrates transistor designers' general preference to keep voltage threshold profiles relatively flat over the width of a transistor so that a transistor will work with approximately the same threshold voltage regardless of its width and length.
A related effect is the reversed short channel effect (RSCE). This effect is independent of transistor width and is instead concerned with the transistor length. Where transistor widths are great in a NMOS device (for example in excess of 10 microns), but lengths are short, boron diffusion from the p-well below the lower channel area tends to increase the concentration of boron at the channel surface. This makes the transistor harder to invert requiring a higher threshold voltage to get the same inversion. This phenomenon, referred to as "roll-up," is demonstrated in FIG. 2 which depicts a graph of threshold voltage (V.sub.t) versus channel length (L) illustrating the problem of RSCE. FIG. 1 depicts a graph of threshold voltage (V.sub.4) versus channel width (W) illustrating the problem of RNCE. The graph 200 plots two lines. The phantom line 201 represents a flat ideal profile desired by device designers so that control is uniform across the whole length of a transistor. The other line (curve) 202 represents the voltage threshold profile for a NMOS device. As can be seen in the plot, short channel transistors as susceptible to roll-up; that is, the voltage threshold increases for short channel transistors. Again, as discussed with RNCE, boron migration from the p-well into the lower channel region towards the gate oxide exacerbates this RSCE roll-up problem.
Accordingly, semiconductor device structures and fabrication techniques that reduce RNCE and RSCE and/or otherwise optimize the use of shallow trench isolation in integrated circuit fabrication would be desirable. cl SUMMARY OF THE INVENTION
To achieve the foregoing, the present invention provides a technique for fabrication of a nitrided gate oxide and STI oxide liner in a semiconductor device. One application of the present invention is to suppress both boron penetration into STI oxide and the RNCE in CMOS devices by introducing nitrogen to the STI edges of the p-well. This technique improves isolation performance and is also effective to harden the oxide. Nitridization of the STI liner may be conducted on its own or in combination with gate oxide nitridization, both with beneficial effect with regard to the RNCE. The nitridization may also be focussed on the channel region of the gate oxide in particular in order to mitigate RSCE.
In one aspect, the invention provides a process for forming a shallow trench isolation in a semiconductor device. The process involves depositing a pad oxide layer on the surface of a silicon substrate, forming a shallow trench in the substrate, and forming an oxide liner in the shallow trench. Nitrogen is implanted into the oxide trench liner and underlying substrate silicon at the oxide/silicon interface, and the trench is filled with oxide.
In another aspect, the invention provides a shallow trench isolation in a semiconductor device. The device includes a pad oxide layer on the surface of a silicon substrate and a shallow trench in the substrate separating two or more device regions. The shallow trench includes an oxynitride/silicon nitride liner and is filled with oxide.
In another aspect, the invention provides a method of reducing reverse narrow channel effect in a semiconductor device having a shallow trench isolation separating n-well and p-well regions in a silicon substrate. The method involves implanting nitrogen into a oxide trench liner of the shallow trench isolation and underlying substrate silicon at the oxide/silicon interface, filling the trench with oxide to form a shallow trench isolation, and forming a gate oxide on the substrate and shallow trench isolation. The gate oxide over the n-well region in the substrate is masked, and nitrogen is implanted into an unmasked portion of the gate oxide to form an oxynitride layer overlying a silicon nitride layer. The mask is removed and the oxide and oxynitide portions of the original oxide layer on the substrate and further oxidized.
In another aspect, the invention provides a method of reducing reverse short channel effect in a semiconductor device. The method involves forming source, drain and channel regions in a silicon substrate, and forming an oxide layer on the substrate over the source, drain and channel regions. Nitrogen is implanted into at least a portion of the oxide layer overlying the channel region and underlying substrate silicon at the oxide/silicon interface to form an oxynitride layer overlying a silicon nitride layer, and the oxide and oxynitride portions of the original oxide layer on the substrate are further oxidized.
These and other features and advantages of the present invention are described below with reference to the drawings.